1. Field of the Invention
The present invention relates to a method of forming a dual damascene structure on a semiconductor wafer, and more particularly, to a method of forming a dual damascene structure with no voids inside it on a semiconductor wafer.
2. Description of the Prior Art
A dual damascene process is a method of forming a conductive wire coupled with a via plug. The dual damascene structure is used to connect devices and wires in a semiconductor wafer and is insulated with other devices by the inter-layer dielectrics (ILD) around it. At the end of the dual damascene process, a chemical mechanical polish (CMP) process is always performed to planarize the surface of the semiconductor wafer so that the subsequent deposition and photolithographic processes perform well on the wafer and so that good multilevel interconnects can be formed. As a result, the dual damascene structure is widely applied in the manufacturing process of integrated circuits. As integrated circuit technology advances, improving the yield of the dual damascene structure is an important issue in the manufacturing process of integrated circuits at the present time.
Please refer to FIG. 1 to FIG. 6. FIG. 1 to FIG. 6 are schematic diagrams of the process of forming a dual damascene structure 42 on a semiconductor wafer 10 according to the prior art. As shown in FIG. 1, the semiconductor wafer 10 comprises a substrate 12, a conductive layer 14 positioned on a predetermined area of the substrate 12, a first inter layer dielectric (ILD) 16 formed of silicon oxide and positioned on the substrate 12 and the conductive layer 14, a silicon nitride (SiN) layer 18 positioned on the ILD 16, and a second inter layer dielectric (ILD) 20 formed of silicon oxide and positioned on the silicon nitride layer 18. The ILD 16, the silicon nitride layer 18 and the ILD 20 are deposited serially using a plasma-enhanced chemical vapor deposition (PECVD) process.
In the prior art method of forming the dual damascene structure 42, a lithographic process is performed first to form a photoresist layer 22 evenly on the ILD 20 with an opening 24 positioned above the conductive layer 14, which extends down to the ILD 20. The opening 24 is used to define the via pattern. As shown in FIG. 2, an anisotropic dry-etching process is then performed along the opening 24 to vertically remove the ILD 20 and the silicon nitride layer 18 positioned under the opening 24 down to the ILD 16 which forms a hole 26. Then a resist stripping process is performed to completely remove the first photoresist layer 22.
As shown in FIG. 3, a lithographic process is performed again to form a photoresist layer 28 evenly on the ILD 20 with two line-shaped openings 30 in the photoresist layer 28 to define the wiring line pattern for connecting transistors. As shown in FIG. 4, a dry-etching process is then performed along the line-shaped openings 30 and hole 26 to vertically remove the ILD 20 and ILD 16 positioned under the openings 30 and the hole 26 down to the silicon nitride layer 18 and the substrate 12 so as to form two line-shaped recesses 32 and a via hole 34 respectively.
As shown in FIG. 5, the photoresist layer 28 is then removed completely. A metallic layer 36 is then deposited on the semiconductor wafer 10 to fill the line-shaped recesses 32 and the via hole 34 so as to form conductive wires 38 and a via plug 40. As shown in FIG. 6, a chemical mechanical polish (CMP) process is employed to remove the metallic layer 36 positioned on the ILD 20 and to align the upper surface of the conductive wire 38 with the surface of the ILD 20, completing the dual damascene structure 42.
In the prior art method of forming the dual damascene structure 42, the width (W) at the bottom of the via hole 34 is much smaller than its height (H), so the via hole 34 has a higher high aspect ratio. When the via hole 34 is filled with the metallic layer 36, the metallic layer 36 will overhang from the upper corners of the via hole 34 and further restrict the hole 34, causing voids 44 to form inside it. The resistance of the via plug 40 will increase because of the voids 44 in the via plug 40, resulting in an unstable electrical current in the dual damascene structure 42 which can effect the electrical performance of the entire semiconductor integrated circuit. Furthermore, because of the voids 44 inside the via plug 40, the structure of the dual damascene may be weakened and so more easily destroyed in subsequent processes.